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ltm8008 1 8008fa typical a pplica t ion fea t ures descrip t ion 72v in , 6 output dc/dc sepic module regulator the ltm ? 8008 is a 72v in , module ? sepic converter with six post regulators. the sepic controllers fxed frequency, current-mode architecture results in stable operation over a wide range of supply and output voltages and features soft-start and frequency foldback functions to limit inductor current during start-up and output short-circuit. the ltm8008 also includes six high performance, fxed output ldos for post-regulation: one 5v at 500ma, one 3.3v at 300ma, and four 5v at 150ma. the output of the sepic controller is internally set to 5.6v for optimal ef- fciency. in addition to providing these outputs, the sepic converter can supply up to an additional 500ma to the system load. the ltm8008 is packaged in a thermally enhanced, compact (15mm 15mm) and low profle (2.82mm) over-molded land grid array (lga) package suitable for automated assembly by standard surface mount equipment. the ltm8008 is pb-free and rohs compliant. a pplica t ions n one sepic converter with six linear regulators n wide input voltage range: 3v to 72v , 6v start n wide operating temperature: C40c to 150c (h-grade) n current mode control provides excellent transient response n programmable operating frequency (100khz to 1mhz) with one external resistor n synchronizeable to an external clock n programmable input undervoltage lockout with hysteresis n programmable soft-start n small 15mm 15mm 2.82mm lga package n automotive converters n industrial converters n telecom power supplies gnd run 8008 ta01 ltm8008 v in v in 3v to 72v ss sync rt v c spv v out1 v out2 v out3 v out4 v out5 v out6 intv cc 3.3v at 300ma 5v at 150ma 5v at 150ma 5v at 150ma 5v at 150ma 5v at 500ma sw 10f sbr3u100lp-7 4.7f 4.7f l1: coupled inductor, coilcraft msd1278t-472ml 22f 10f 10f 10f 10f 10f 22nf 42.2k 4.99k l1a 4.7h l1b 4.7h l , lt, ltc, ltm, linear technology, the linear logo and module are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. six output dc/dc module regulator
ltm8008 2 8008fa p in c on f igura t ion a bsolu t e maxi m u m r a t ings v in , sw ..................................................................... 80v ru n .................................................................... in tv cc sync, spv, intv cc .................................................... 8v v c , ss ......................................................................... 3v rt ............................................................................ 1. 5v v out1,2,3,4,5,6 relative to spv ................................... 20 o perating internal temperature (note 2) .................................................. C 40c to 150c storage temperature range .................. C 55c to 150c maximum solder temperature .............................. 24 5c (note 1) lkjhgfedcba 1 2 3 4 5 6 7 8 10 9 11 spv v out2 v out3 v out4 v out5 v out6 spv v out1 intv cc run v c ss rt sw sync gnd bank 1 bank 3 bank 2 v in lga package 121-lead (15mm 15mm 2.82mm) top view t jmax = 150c, ja = 9.6c/w, jctop = 12.2c/w, jcbottom = 0.5c/w, jcboard = 1.6c/w values determined per jesd51-9, max output power weight = 1.4 grams e lec t rical c harac t eris t ics o r d er i n f or m a t ion the l denotes specifcations that apply over the full operating temperature range, v in = 14v, run = 14v, otherwise specifcations are at t a = 25c (note 2) parameter conditions min typ max units minimum v in operating voltage l 3 v minimum v in start voltage v in rising l 6 v v in shutdown i q run = 0v 70 a v in operating i q v c = 0.3v, r t = 41.2k 1.6 2.2 ma spv regulation voltage 5.6 v spv overvoltage threshold 6.1 v v c source current spv = 0v, v c = 1.5v C15 a v c sink current spv = 6v, v c = 1.5v 12 a lead free finish tray part marking package description temperature range ltm8008hv#pbf ltm8008hv#pbf ltm8008v 121-lead (15mm 15mm 2.82mm) lga C40c to 150c consult ltc marketing for parts specifed with wider operating temperature ranges. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ this product is only offered in trays. for more information go to: http://www.linear.com/packaging/
ltm8008 3 8008fa note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. the l denotes specifcations that apply over the full operating temperature range, v in = 14v, run = 14v, otherwise specifcations are at t a = 25c (note 2) parameter conditions min typ max units switching frequency r t = 140k to gnd r t = 10.5k to gnd 100 1 khz mhz minimum off time 220 ns minimum on time 220 ns sync input low 0.4 v sync input high 1.5 v ss sourcing current ss = 0v C10 a ss sink current under fault ss = 1v 0.7 ma run threshold to stop switching l 1.15 1.21 1.26 v run bias current low 2 a run bias current high run = 1.3v 0.1 a sw current limit l 7.4 8.2 9.0 a sw r ds(on) 35 m? v out1 output voltage 1ma < i load < 500ma l 4.95 4.9 5 5.05 5.1 v v v out1 load regulation i load = 1ma to 500ma l 12 25 50 mv mv v out1 rms output noise r t = 41.2k, i load = 500ma, bw = 100hz to 100khz 20 v rms v out1 current limit l 520 ma v out1 reverse output current spv = 0, v out1 = 5v 10 a v out2,3,4,5 output voltage 1ma < i load < 150ma l 4.95 4.9 5 5.05 5.1 v v v out2,3,4,5 load regulation i load = 1ma to 150ma l 9 25 50 mv mv v out2,3,4,5 rms output noise r t = 41.2k, i load = 150ma, bw = 100hz to 100khz 20 v rms v out2,3,4,5 current limit l 160 ma v out2,3,4,5 reverse output current spv = 0, v out2,3,4,5 = 5v 10 20 a v out6 output voltage 1ma < i load < 300ma l 3.267 3.234 3.3 3.333 3.366 v v v out6 load regulation i load = 1ma to 300ma l 7 15 33 mv mv v out6 rms output noise r t = 41.2k, i load = 300ma, bw = 100hz to 100khz 20 v rms v out6 current limit l 320 ma v out6 reverse output current spv = 0, v out1 = 5v 10 20 a e lec t rical c harac t eris t ics note 2: the ltm8008hv is guaranteed to meet performance specifcations from C40c to 150c internal operating temperature range. note that the maximum internal temperature is determined by specifc operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors.
ltm8008 4 8008fa typical p er f or m ance c harac t eris t ics spv vs percentage of ldo load v out1 vs temperature full load v out2,3,4,5 vs temperature full load v out6 vs temperature full load spv vs temperature (front page schematic) v out1 current limit vs temperature v out1 vs load v out2,3,4,5 vs load v out6 vs load load current (ma) 0 v out1 (v) 5.018 5.002 5.014 5.010 5.006 5.016 5.012 5.008 5.004 5.000 8008 g01 500 200 400 100 300 maximum rated ldo load (%) 0 spv (v) 5.625 5.620 5.615 5.610 5.605 25 50 75 8008 g04 100 temperature (c) ?40 v out6 (v) 3.33 3.32 3.31 3.30 3.27 3.28 3.29 8008 g07 110 60 10 temperature (c) ?40 spv (v) 5.67 5.65 5.63 5.61 5.59 5.57 5.53 5.55 8008 g08 110 60 10 no ldo load full rated ldo load 1600 1400 1200 1000 0 200 400 600 800 ?40 0 140120 20 ?20 806040 100 temperature (c) current limit (ma) 8008 g09 short-circuit v out drops 1% temperature (c) ?40 0 v out1 (v) 5.050 4.975 5.025 5.000 4.950 8008 g05 140120 20 ?20 806040 100 temperature (c) ?40 v out (v) 5.05 5.04 5.03 5.02 5.01 5.00 4.95 4.96 4.97 4.98 4.99 8008 g06 110 60 10 load current (ma) 0 v out (v) 5.022 5.020 5.018 5.014 5.010 5.016 5.012 5.008 5.006 8008 g02 150 50 100 load current (ma) 0 v out6 (v) 3.302 3.290 3.298 3.294 3.300 3.296 3.292 3.288 8008 g03 300 200 10050 250 150
ltm8008 5 8008fa typical p er f or m ance c harac t eris t ics run threshold vs temperature run current vs run voltage input current vs percentage of ldo load (front page schematic) temperature rise vs percentage of ldo load (front page schematic, measured on dc1630a demo board) v out2,3,4,5 current limit vs temperature v out6 current limit vs temperature v in pin current vs temperature (no load) temperature (c) ?40 0 threshold voltage (v) 1.210 1.195 1.205 1.200 1.190 8008 g13 140120 20 ?20 806040 100 maximum rated ldo load (%) 0 input current (ma) 900 800 700 600 500 400 300 200 100 0 8008 g15 100 40 80 20 60 24v in 12v in maximum rated ldo load (%) 0 temperature rise (c) 35 30 25 20 15 10 5 0 8008 g16 100 40 80 20 60 24v in 12v in run voltage (v) 0 run current (a) 25 5 15 20 10 0 8008 g14 10 4 8 2 6 600 500 100 0 200 300 400 ?40 0 140120 20 ?20 806040 100 temperature (c) current limit (ma) 8008 g10 short-circuit v out drops 1% 1000 900 800 700 0 200 400 100 300 600 500 ?40 0 140120 20 ?20 806040 100 temperature (c) current limit (ma) 8008 g11 short-circuit v out drops 1% 150 140 130 120 60 70 90 80 110 100 ?40 0 140120 20 ?20 806040 100 temperature (c) input current (a) 8008 g12 24v in 12v in
ltm8008 6 8008fa p in func t ions v in (k4, l4): input supply pin. must be locally bypassed with a 0.22f or larger capacitor placed close to the pin. run (f1, f2): shutdown and undervoltage detect pin. an accurate 1.21v (nominal) falling threshold with ex- ternally programmable hysteresis detects when power is okay to enable switching. rising hysteresis is generated by the external resistor divider and an accurate internal 2a pull-down current. an undervoltage condition resets soft-start. tie to 0.4v or less to disable the device and reduce v in quiescent current below 70a. tie to intv cc if this function is not used. gnd (bank 1): ground. tie these gnd pins to a local ground plane under the ltm8008 and the circuit components. in most applications, the bulk of the heat fow out of the ltm8008 is through these pads, so the printed circuit design has a large impact on the thermal performance of the part. see the pcb layout and thermal considerations sections for more details. sync (k3, l3): frequency synchronization pin. it is used to synchronize the switching frequency to an external clock. if this feature is used, an r t resistor should be chosen to program a switching frequency 20% lower than the sync pulse frequency. tie the sync pin to gnd if this feature is not used. see the synchronization section in applications information. rt (j1, j2): the rt pin is used to program the switching frequency of the ltm8008 by connecting a resistor from this pin to ground. table 1 gives the resistor values that correspond to the resultant switching frequency. minimize the capacitance at this pin. ss (h1, h2): soft-start pin. this pin modulates the com- pensation pin voltage (v c ) clamp. the soft-start interval is set with an external capacitor. the pin has a 10a (typical) pull-up current source to an internal 2.5v rail. the soft- start pin is reset to gnd by an undervoltage condition at run, an intv cc undervoltage or overvoltage condition or an internal thermal lockout. v c (g1, g2): error amplifer compensation pin. this is used to stabilize the voltage loop with an external rc network. intv cc (e1, e2): regulated supply for internal loads. this is derived from v in and spv; it must be bypassed with at least a 4.7f capacitor placed close to the pin. spv (a1, b1, a11, b11): sepic output voltage. this is connected to the internal sepic feedback network and is used to power the six post regulators. it must be locally bypassed by at least 22f. apply a bypass capacitor at each set of pins. v out1 (bank 2): output of the 5v, 500ma linear post regulator. it must be locally bypassed with at least 22f. v out2 (a10, b10): output of one of the four 5v, 150ma linear post regulators. it must be bypassed with at least 10f. v out3 (a8, b8): output of one of the four 5v, 150ma linear post regulators. it must be bypassed with at least 10f. v out4 (a6, b6): output of one of the four 5v, 150ma linear post regulators. it must be bypassed with at least 10f. v out5 (a5, b5): output of one of the four 5v, 150ma linear post regulators. it must be bypassed with at least 10f. v out6 (a2, a3, b2): output of the 3.3v, 300ma linear post regulator. it must be bypassed by at least 10f. sw (bank 3): sepic converter switch. this is the drain of the internal power switching mosfet.
ltm8008 7 8008fa s i m pli f ie d b lock diagra m linear pre-regulator spv 5.6v gnd intv cc 8008 bd sepic controller linear post regulators sw q1 external power components run v in ss sync rt v c v out5 5v at 150ma v out4 5v at 150ma v out3 5v at 150ma v out2 5v at 150ma v out6 3.3v at 300ma v out1 5v at 500ma ? ? o pera t ion the ltm8008 is a sepic equipped with six high perfor - mance linear post regulators. the device contains the sepic power mosfet, controller, linear regulators and optimized support circuitry. the current limit for the sepic converter is internally set to 8.2a. the output of the sepic converter is internally set to 5.6v, which is the optimal voltage for running the six post regulators at the best combination of effciency, ripple rejection and thermal performance. the sepic converter is equipped with several control pins. these include run for enabling and sequencing, ss for soft-start control, sync for frequency synchronization, rt for setting the operating frequency and v c for frequency compensation. there are also power ports, v in , intv cc , spv and the six post regulator outputs, v out1,2,3,4,5,6 , as well as the sepic converter switch node, sw. of the six linear post regulators, one produces 5v at 500ma, a second produces 3.3v at 300ma and the remaining four provide 5v at 150ma each. each one is individually equipped with overcurrent, reverse voltage and thermal protection.
ltm8008 8 8008fa a pplica t ions i n f or m a t ion running input voltage versus start voltage in normal operation the ltm8008 sepic converter output spv is used to run the intv cc internal biasing through a rectifying diode (see the block diagram). this allows the internal mosfet driver q1 and other circuitry to be properly biased even when the input voltage falls as low as 3v. at start-up, however, the spv voltage is low and intv cc is derived from v in through a linear regulator. in order to properly bias the ltm8008 internal circuitry at start-up, v in must rise to at least 6v. main control loop the ltm8008 uses a fxed frequency, current mode con - trol scheme to provide excellent line and load regulation. at the start of each oscillator cycle, a latch turns on the internal power mosfet switch. the switch current fows through an internal current sensing resistor and generates a voltage proportional to the switch current. this current sense voltage is added to a stabilizing slope compensation ramp and the resulting sum is compared with the voltage on the v c pin. when the stabilized current sense voltage exceeds the level of the v c pin, the internal latch is reset, turning off the power switch. the level at the v c pin is an amplifed version of the difference between the feedback voltage and the reference voltage. in this manner, the error amplifer sets the correct peak switch current level to keep the output in regulation. the ltm8008 is also equipped with a switch current limit function. if the detected current is higher than 8.2a, typical, the internal circuitry will turn off q1 for the rest of the switching cycle. the ltm8008 has overvoltage protection functions to pro - tect the converter from excessive output voltage overshoot during start-up or recovery from a short-circuit condition. if the output voltage exceeds the targeted set point by 8%, internal circuitry will actively inhibit switching for the duration of an output overvoltage condition. programming turn-on and turn-off thresholds with the run pin the run pin controls whether the ltm8008 is enabled or shut down. low power circuitry allows the user to ac - curately program the supply voltage at which the sepic converter turns on and off. the falling value can be ac- curately set by the resistor divider network composed of r3 and r4 shown in figure 1. figure 1. the ltm8008 turn-on and turn-off thresholds are set by a simple resistor network ltm8008 8008 f01 v in run r4 r3 if run is above 1.21v, the ltm8008 is running. below 1.21v and above 0.7v, the ltm8008 is off and the run pin sinks a hysteresis current (typically 2a). below 0.7v, the ltm8008 is not switching and is in a low power state, drawing less than 70a at v in . the typical falling threshold voltage and rising threshold voltage can be calculated by the following equations: v vin,falling = 1.21 ? r3 + r4 ( ) r4 v vin,rising = 2a ? r3 + v in,falling for applications where the run pin is not used, the run pin can be connected directly to the input voltage intv cc for always-on operation. intv cc regulator bypassing and operation an internal, low dropout (ldo) voltage regulator produces the intv cc supply which powers the internal circuitry during start-up or whenever spv is low. the ltm8008 contains an undervoltage lockout comparator and an overvoltage lockout comparator for the intv cc supply. the intv cc undervoltage (uv) function protects the internal circuitry from attempting to operate in a brown-out condition, while the overvoltage (ov) function protects the gate of the power mosfet and excessive power dissipation within the ltm8008 in the case of a fault. when intv cc is below the uv threshold, or above the ov threshold, switching stops and the soft-start operation will be triggered. the intv cc regulator must be bypassed to ground im- mediately adjacent to the ltm8008 pins with a minimum of a 4.7f ceramic capacitor. good bypassing is neces - sary to supply the high transient currents required by the mosfet gate driver.
ltm8008 9 8008fa a pplica t ions i n f or m a t ion in an actual application, most of the intv cc supply current is used to drive the gate capacitance of the power mosfet. the power dissipation can be a signifcant concern when the internal mosfet is being driven at a high frequency and the v in voltage is high. it is important to limit the power dissipation of the mosfet and/or adjust the operating frequency so the ltm8008 does not exceed its maximum junction temperature rating. operating frequency and synchronization the choice of operating frequency may be determined by on-chip power dissipation, otherwise it is a trade-off between effciency and component size. low frequency operation improves effciency by reducing gate drive cur - rent and mosfet and diode switching losses. however, lower frequency operation requires a physically larger inductor. switching frequency also has implications for loop compensation. the ltm8008 uses a constant-frequency architecture that can be programmed over a 100khz to 1mhz range with a single external resistor from the rt pin to gnd. the rt pin must have an external resistor to gnd for proper operation of the ltm8008. a table for selecting the value of r t for a given operating frequency is shown in table 1. table 1. timing resistor (r t ) value oscillator frequency (khz) r t (k) 100 140 200 63.4 300 41.2 400 30.9 500 24.3 600 19.6 700 16.5 800 14 900 12.1 1000 10.5 the operating frequency of the ltm8008 can be synchro - nized to an external clock source. by providing a digital clock signal into the sync pin, the ltm8008 will operate at the sync clock frequency. if this feature is used, an r t resistor should be chosen to program a switching frequency 20% slower than sync pulse frequency. the sync pulse should have a minimum pulse width of 200ns. tie the sync pin to gnd if this feature is not used. duty cycle considerations switching duty cycle is a key variable defning converter operation. as such, its limits must be considered. minimum on-time is the smallest time duration that the ltm8008 is capable of turning on the power mosfet. this time is generally about 220ns (typical) (see minimum on-time in the electrical characteristics table). in each switching cycle, the ltm8008 keeps the power switch off for at least 220ns (typical) (see minimum off-time in the electrical characteristics table). soft-start the ltm8008 contains several features to limit peak switch currents and output voltage (v out ) overshoot during start-up or recovery from a fault condition. the primary purpose of these features is to prevent damage to external components or the load. high peak switch currents during start-up may occur in switching regulators. since v out is far from its fnal value, the feedback loop is saturated and the regulator tries to charge the output capacitor as quickly as possible, resulting in large peak currents. a large surge current may cause inductor saturation or power switch failure. the ltm8008 addresses this mechanism with the ss pin. the ss circuit reduces the power mosfet current by pull - ing down the v c pin. in this way the ss allows the output capacitor to charge gradually toward its fnal value while limiting the start-up peak currents. the inductor current slew rate is limited by the soft-start function. besides start-up, soft-start can also be invoked by the following faults: 1. int v cc overvoltage 2. int v cc undervoltage 3. thermal lockout any of these three faults will cause the ltm8008 to stop switching immediately and discharge the ss pin. when all faults are cleared and the ss pin has been discharged below 0.2v, a 10a current source will start charging the
ltm8008 10 8008fa a pplica t ions i n f or m a t ion ss pin, initiating a soft-start operation. the soft-start in- terval is set by the soft-start capacitor selection according to the equation: t ss = c ss ? 1.25v 10a thermal lockout if ltm8008 internal temperature reaches 165c (typical), the part will go into thermal lockout. the power switch will be turned off. a soft-start operation will be triggered. the part will be enabled again when the die temperature has dropped by 5c (nominal). loop compensation loop compensation determines the stability and transient performance. the ltm8008 uses current mode control to regulate the output which simplifes loop compensation. the optimum values depend on the converter topology, the component values and the operating conditions (including the input voltage, load current, etc.). to compensate the feedback loop of the ltm8008, a series resistor-capacitor network is usually connected from the v c pin to gnd. figure 2 shows the typical v c compensation network. for most applications, the capacitor c c1 should be in the range of 1nf to 47nf, and the resistor r c should be in the range of 2.5k to 50k. a small capacitor c c2 is often connected in parallel with the r c compensation network to attenuate the v c voltage ripple induced from the output voltage ripple through the internal error amplifer. the parallel capacitor usually ranges in value from 10pf to 100pf. a practical approach to design the compensation network is to start with one of the circuits in this data sheet that is similar to your application, and tune the compensation network to optimize the performance. stability should then be checked across all operating conditions, including load current, input voltage and temperature. board layout the high speed operation of the ltm8008 demands careful attention to board layout and component placement. the gnd pads of the package are the primary heat path of the device, and are important for thermal management. there- fore, it is crucial to achieve a good electrical and thermal contact between the gnd pads and the ground plane of the board. for the ltm8008 to deliver its full output power, it is imperative that a good thermal path be provided to dissipate the heat generated within the package. it is recommended that multiple vias in the printed circuit board be used to conduct heat away from the ltm8008 and into a copper plane with as much area as possible. to prevent radiation and high frequency resonance problems, proper layout of the components connected to the ltm8008 is essential, especially the power paths with higher di/dt. the high di/dt loop should be kept as tight as possible to reduce inductive ringing. in the sepic confguration, the high di/dt loop contains the power mosfet, sense resistor, output capacitor, schottky diode and the coupling capacitor. keep the circuit path among these components as short as possible. the ltm8008 is a switching power supply, so care must be taken to minimize emi and ensure proper operation. even with the high level of integration, you may fail to achieve specifed operation with a haphazard or poor layout. see figure 3 for a suggested layout. ensure that the grounding and heat-sinking are acceptable. here are additional tips to follow: 1. place the l1, r t and v c components as close as pos- sible to their respective pins. 2. place the c in , c intvcc , spv and c out capacitors as close as possible to their respective pins. if more than one capacitor is required in parallel, place as many of the electrically paralleled capacitors as close as possible to their respective pin. 3. place the c in and c out capacitors such that their ground currents follow a path as short as possible. figure 2. a typical compensation network 8008 f02 r c c c2 v c c c1
ltm8008 11 8008fa gnd gnd spv spv power diode spv control discretes ldo output capacitors ldo output capacitor flying capacitor coupled inductor l1 sw v in v in c intvcc c in c out c out a pplica t ions i n f or m a t ion 4. connect all of the gnd connections to as large a copper pour or plane area as possible on the top layer. avoid breaking the ground connection between the external components and the ltm8008. 5. for good heatsinking, use vias to connect the gnd cop- per area to the board s internal ground planes. liberally distribute these gnd vias to provide both a good ground connection and thermal path to the internal planes of the printed circuit board. pay attention to the location and density of the thermal vias in figure 3. the ltm8008 can beneft from the heat-sinking afforded by vias that connect to internal gnd planes at these locations, due to their proximity to internal power handling components. the optimum number of thermal vias depends upon the printed circuit board design. for example, a board might use very small via holes. it should employ more thermal vias than a board that uses larger holes. post regulator output capacitance and transient response the ltm8008 linear post regulators are designed to be stable with a wide range of output capacitors. the esr of the output capacitor affects stability, most notably with small capacitors. the output transient response will be a function of output capacitance. larger values of output capacitance decrease the peak deviations and provide im - proved transient response for larger load current changes. bypass capacitors, used to decouple individual components powered by the post regulators, will increase the effective output capacitor value. extra consideration must be given to the use of ceramic capacitors. ceramic capacitors are manufactured with a variety of dielectrics, each with dif- ferent behavior across temperature and applied voltage. the most common dielectrics used are specifed with eia temperature characteristic codes of z5u, y5v, x5r and figure 3. layout showing suggested external components, gnd plane and interconnect/thermal vias
ltm8008 12 8008fa a pplica t ions i n f or m a t ion x7r. the z5u and y5v dielectrics are good for providing high capacitances in a small package, but they tend to have strong voltage and temperature coeffcients. when used with a 5v regulator, a 16v 10f y5v capacitor can exhibit an effective value as low as 1f to 2f for the dc bias voltage applied and over the operating temperature range. the x5r and x7r dielectrics result in more stable characteristics and are more suitable for use as the output capacitor. the x7r type has better stability across tem - perature, while the x5r is less expensive and is available in higher values. care still must be exercised when using x5r and x7r capacitors; the x5r and x7r codes only specify operating temperature range and maximum capacitance change over temperature. capacitance change due to dc bias with x5r and x7r capacitors is better than y5v and z5u capacitors, but can still be signifcant enough to drop capacitor values below appropriate levels. capacitor dc bias characteristics tend to improve as component case size increases, but expected capacitance at operating voltage should be verifed. voltage and temperature coeffcients are not the only sources of problems. some ceramic capacitors have a piezoelectric response. a piezoelectric device generates voltage across its terminals due to mechanical stress, similar to the way a piezoelectric accelerometer or micro- phone works. for a ceramic capacitor, the stress can be induced by vibrations in the system or thermal transients. the resulting voltages produced can cause appreciable amounts of noise, especially when a ceramic capacitor is used for noise bypassing. post regulator thermal considerations the power handling capability of the post regulators will be limited by the maximum rated junction temperature (150c). the power dissipated by each post regulator is approximately the output current multiplied by the input/ output voltage differential: (i out ) ? (spv C v out ). the post regulators have internal thermal limiting de- signed to protect the device during overload conditions. for continuous normal conditions, the maximum junction temperature rating of 150c must not be exceeded. it is important to give careful consideration to all sources of thermal resistance from junction-to-ambient. additional heat sources mounted nearby must also be considered. for surface mount devices, heat sinking is accomplished by using the heat spreading capabilities of the pc board and its copper traces. copper board stiffeners and plated through-holes can also be used to spread the heat gener - ated by power devices. protection features the linear post regulators incorporate several protection features. in addition to the normal protection features associated with monolithic regulators, such as current limiting and thermal limiting, the devices are protected against reverse input voltages, reverse output voltages and reverse voltages from output to input. current limit protection and thermal overload protection are intended to protect the device against current overload conditions at the output of the device. for normal operation, the junction temperature should not exceed 150c. when any of the v out pins are forced above the spv pin of the ltm8008, input current to the corresponding post regulator will typically drop to less than 2a. the output of the linear post regulators can be pulled below ground without damaging the device. if the input is left open-cir - cuit or grounded, the output can be pulled below ground by 20v. the outputs will act like a large resistor, typically 500k or higher, limiting current fow to less than 100a. in the case of a short circuit, the output will source the short-circuit current of the device and will protect itself by thermal limiting.
ltm8008 13 8008fa p ackage descrip t ion p ackage p ho t o pin name a1 spv a2 v out6 a3 v out6 a4 gnd a5 v out5 a6 v out4 a7 gnd a8 v out3 a9 gnd a10 v out2 a11 spv b1 spv b2 gnd b3 v out6 b4 gnd b5 v out5 b6 v out4 b7 gnd b8 v out3 b9 gnd b10 v out2 b11 spv pin assignment table (arranged by pin number) pin name c1 gnd c2 gnd c3 gnd c4 gnd c5 gnd c6 gnd c7 gnd c8 gnd c9 gnd c10 gnd c11 gnd d1 gnd d2 gnd d3 gnd d4 gnd d5 gnd d6 gnd d7 gnd d8 gnd d9 gnd d10 v out1 d11 v out1 pin name e1 intv cc e2 intv cc e3 gnd e4 gnd e5 gnd e6 gnd e7 gnd e8 gnd e9 gnd e10 v out1 e11 v out1 f1 run f2 run f3 gnd f4 gnd f5 gnd f6 gnd f7 gnd f8 gnd f9 gnd f10 gnd f11 gnd pin name g1 v c g2 v c g3 gnd g4 gnd g5 gnd g6 gnd g7 gnd g8 gnd g9 gnd g10 gnd g11 gnd h1 ss h2 ss h3 gnd h4 gnd h5 gnd h6 gnd h7 gnd h8 gnd h9 gnd h10 gnd h11 gnd pin name j1 rt j2 rt j3 gnd j4 gnd j5 gnd j6 gnd j7 gnd j8 sw j9 sw j10 sw j11 sw k1 gnd k2 gnd k3 sync k4 v in k5 gnd k6 gnd k7 gnd k8 sw k9 sw k10 sw k11 sw pin name l1 gnd l2 gnd l3 sync l4 v in l5 gnd l6 gnd l7 gnd l8 sw l9 sw l10 sw l11 sw
ltm8008 14 8008fa notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters land designation per jesd mo-222, spp-010 5. primary datum -z- is seating plane 6. the total number of pads: 121 4 3 details of pad #1 identifier are optional, but must be located within the zone indicated. the pad #1 identifier may be either a mold or marked feature symbol aaa bbb eee tolerance 0.15 0.10 0.05 2.72 ? 2.92 detail b detail b substrate mold cap 0.27 ? 0.37 2.45 ? 2.55 // bbb z z 15 bsc package top view 15 bsc 4 pad 1 corner x y aaa z aaa z detail a 12.70 bsc 1.27 bsc 12.70 bsc l k j h g f e d c b package bottom view 3 pads see notes a 12345678 10 9 11 suggested pcb layout top view 0.000 1.270 1.270 2.540 2.540 3.810 3.810 5.080 5.080 6.350 6.350 6.350 6.350 3.810 3.810 5.080 5.080 2.540 2.540 1.270 1.270 0.000 lga 121 1010 rev a ltmxxxxxx module tray pin 1 bevel package in tray loading orientation component pin ?a1? pad 1 dia (0.630) lga package 121-lead (15mm 15mm 2.82mm) (reference ltc dwg# 05-08-1861 rev a) 0.955 1.585 0.955 1.585 detail a dia (0.630) 121x s yxeee p ackage descrip t ion
ltm8008 15 8008fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 2/11 removed run threshold to i q to fall below 1a spec 3
ltm8008 16 8008fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2010 lt 0211 rev a? printed in usa r ela t e d p ar t s part number description comments ltm8027 60v, 4a dc/dc module regulator 4.5v v in 60v, 2.5v v out 24v, 15mm w 15mm w 4.32mm ltc3824 60v, 40a i q dc/dc regulator 4v v in 60v, 100% duty cycle, 200khz to 600khz for an h-grade product portfolio go to: http://cds.linear.com/docs/information%20card/ltc_h_grade_products_web.pdf typical a pplica t ion gnd run 8008 ta02 ltm8008 v in v in 3v to 72v ss sync rt v c spv v out1 v out2 v out3 v out4 v out5 v out6 intv cc 3.3v at 300ma 5v at 150ma 5v at 150ma 5v at 150ma 5v at 150ma 5v at 500ma sw 10f sbr3u100lp-7 4.7f 4.7f l1: coupled inductor, coilcraft msd1278t-472ml 22f 10f 10f 10f 10f 10f 22nf 42.2k 4.99k l1a 4.7h l1b 4.7h six output dc/dc module regulator

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